1. Field of the Invention
The present invention relates to a digital image processing apparatus, and more specifically, to a digital image processing apparatus arithmetically processing original image data to enable image data converting processes such as a gradation correction, sharpening of image quality, and processes such as feature extraction from the original image data.
2. Description of the Prior Art
A digital image processing apparatus comprises an image input circuit for inputting image data, an image output circuit for outputting image data, an image memory for storing image data, processing circuit for arithmetically processing image data, a host CPU controlling these circuits and arithmetically processing image data by means of software, and so on. Generally, the host CPU is employed only for those arithmetic processes which can not be effected by the processing circuits. Basic processes are executed by hard logic of the processing circuits. Circuits other than the host CPU transfer image data to and from each other at high speed. However, a data bus is commonly provided which is exclusively used for transferring image data to and from each of the circuits, in consideration of the flexibility of the system.
In such digital image processing apparatus, a processing circuit is adapted to provide a plurality of functions by changing some settings therein, or a plurality of processing circuits are provided and the processing circuits are selected corresponding to the required functions, in order to accomplish these arithmetic functions. Now, a simple process can be effected by a single arithmetic function. However, a process in accordance with a complicated algorithm requires a plurality of different operations or repetition of one operation carried out successively. In order to do so, the processing circuits and processing functions in association with the process must be successively switched. This requires a long period of time. Therefore, the above described sequential processing can not cope with those cases where inputted images to be processed must be continuously processed (real time processing) and where a prescribed processing speed is necessary. In view of the foregoing, in order to increase the speed of operation, a number of necessary processing circuits are provided with input/output data of respective processing circuits coupled to each other in accordance with the order of processing to operate all the processing circuits simultaneously so as to enable simultaneous execution of all required arithmetic functions. This is generally called pipeline processing. In the pipeline processing, the data provided during processing may not be temporarily stored in the image memory, whereby the real time processing of the input data is made possible.
As described above, in order to execute complicated arithmetic processes on real time in a digital image processing apparatus, a number of processing circuits should be provided pipeline coupled with each other. There are two methods of pipeline-coupling of the plurality of processing circuit. Namely, (a) a method in which a plurality of processing circuits are coupled with each other in advance in accordance with a prescribed order, and (b) a method in which a plurality of processing circuits are adapted to be coupled with each other in an arbitrary order.
In the former method (a), unnecessary processing circuits out of the coupled processing circuits should be set in a processing state in which the input data is outputted as it is without any change made thereon, and only necessary circuits are set at prescribed operation state. If the desired order of processing can not be realized, the data provided during the process must be temporarily stored in the image memory.
In the latter method (b), any process can be continuously executed, since only the necessary processing circuits are combined arbitrarily. Therefore, as for the processing functions and processing speed, the latter method is superior to the former one. However, the latter method has disadvantages that the delay time of the whole processing circuit between the input and output data changes dependent on the combination, since the processing circuits are arbitrarily coupled with each other (the delay time may also change in the former method dependent on the processes). Therefore, when the data resulting from the process should be written in the image memory, the image memory for writing (the memory in which data from the image data bus are written: the memory from which the data are read to the image data bus will be hereinafter referred to as an image memory for reading), must use a write address which is delayed from the standard address by the time corresponding to the delay time generated in the processing circuit. When there are a plurality of image memories and each of the image memories operate independently to write image data with different delay times in parallel, a number of write address counters, the number corresponding to the number of image memories to which data should be written, becomes necessary. Namely, one write address counter must be provided for one image memory, which is quite uneconomical.
More detailed description will be given in the following with the reference to the figures.
FIG. 1 shows an example of a structure of a digital image processing apparatus comprising a plurality of processing circuits which can be pipeline-coupled with each other, an image memory, an image input circuit and an image output circuit. The circuits are coupled by a data bus 5 exclusively used for image data. In order to simplify the description, the number of processing circuits is limited to three, and the host CPU which is necessary for control is omitted. As is shown in the figure, the image input circuit 1, the image memory 2, three processing circuits 3a, 3b and 3c and the image output circuit 4 are coupled with each other by the image data bus 5. The three processing circuits 3a, 3b and 3c are pipeline-coupled by signal lines 6a, 6b and 6c.
The image data are inputted from the image input circuit 1 through the image data bus 5 to the image memory 2. As for the output of the image data, the image data read from the image memory 2 enters the image output circuit 4 through the image data bus 5, and they are outputted from the circuit 4 to an external image display apparatus, image recording apparatus, and so on.
The image data is arithmetically processed in various states of operation. For example, in processing image data, only one of the three processing circuits 3a, 3b and 3c operates; two or more of the processing circuits operate in parallel but independently from each other; two of the processing circuits operate pipeline-coupled with each other, and the remaining one does not operate; two of the circuits operate pipeline-coupled with each other, and the remaining one operates in parallel independently; three circuits operate pipeline-coupled with each other, and so on. Other states of operation including pipeline-coupling can be provided by changing combination and order of the processing circuits. In any case, the data read from the image memory 2 or the image data provided from the image input circuit 1 are inputted to the processing circuit (3a, 3b or 3c) as images to be processed through the image data bus 5, and the result of processing is applied to the image memory 2 or to the image output circuit 4 through the image data bus 5.
FIGS. 2 to 5 show connections between the image memory 2 and the processing circuits 3 in various states of arithmetic processing.
In FIG. 2, only one processing circuit 3a out of three processing circuits 3a, 3b and 3c operates. The image to be processed is stored in the image memory 2a, and the read data from the image memory 2a is inputted to the processing circuit 3a through the image data bus 5a and processed in the processing circuit 3a, with the result of processing stored in the image memory 2b.
In FIG. 3, two processing circuits 3a and 3b of the three processing circuits 3a, 3b and 3c operate pipeline-coupled with each other. The image to be processed is stored in the image memory 2a, and it is processed in two processing circuits 3a and 3b, with the result stored in the image memory 2b. Although the processing circuits 3a and 3b are coupled in this example, the combination of the processing circuits 3b and 3c or 3c and 3a are also possible.
In FIG. 4, three processing circuits 3a, 3b and 3c operate pipeline-coupled with each other. In this case also, the image to be processed is stored in the image memory 2a, and it is processed in three processing circuits 3b, 3c and 3a with the result stored in the image memory 2b. The circuits may be coupled in accordance with the order of 3c, 3a and 3b or 3a, 3b and 3c, other than the shown order 3b, 3c and 3a.
In FIG. 5, two processing circuits 3b and 3c of the three processing circuits 3a, 3b and 3c operate pipeline coupled with each other and the remaining processing circuit 3a operates independently. The read data from the image memory 2a are commonly inputted to the processing circuits 3a and 3b to be differently processed, with the results being written in the image memories 2b and 2c, respectively.
As described above, when there are a plurality of processing circuits 3a, 3b and 3c and various combinations of pipeline-coupling are possible between the circuits, the flow of the image data varies widely dependent on the combination of the pipeline-coupling, presence/absence of parallel operation, and selection of the image memory 2 for input and output.
In the foregoing, the delay of data generated in the processing circuits 3a, 3b and 3c is not considered. Generally, when an image to be processed passes through a processing circuit, there will be some delay between the input and output data. The image data is handled in synchronization with a transfer clock of a prescribed period on the image data bus or in each of the processing circuits. The delay mentioned above is represented by the unit of the transfer clock. For example, referring to FIGS. 1 to 5, it is assumed that three processing circuits 3a, 3b and 3c respectively generate delays of l, m, n clocks between the input and output of the image data. In the structure of FIG. 2, there is a delay of l clocks between the read data of the image memory 2a and the write data of the image memory 2b. Similarly, in the structure of FIG. 3, there is a delay of (l+m) clocks, and in the structure of FIG. 4, there is a delay of (l+m+n) clocks. In the structure of FIG. 5, there is a delay of l clocks in the write data of the image memory 2b and there is a delay of (m+n) clocks in the write data of the image memory 2c, respectively.
As described above, only by changing the pipeline structure in the processing circuits or only by changing the processing circuit to be used, the number of stages of delay between input/output data to and from the processing circuit varies widely. Table 1 shows the relation between the combination of the processing circuits employed and the number of delay stages.
TABLE 1 ______________________________________ PROCESSING CIRCUITS EMPLOYED NUMBER OF DELAY STAGES ______________________________________ 3a l 3b m 3c n 3a, 3b l + m 3b, 3c m + n 3c, 3a n + l 3a, 3b, 3c l + m + n ______________________________________
Now, the problem exists in the fact that the write address to be applied to the image memory for writing (the memory in which data are written from the image data bus 5) must correspond the number of delay stages which changes dependent on the structure of the processing circuits 3. When the image memory 2 in operation comprises one memory for reading and one memory for writing as in the structures shown in FIGS. 2 to 4, only one read address counter for generating read address and one write address counter generating write address should be provided. In this case, to change the value of the write address in correspondence with the value of the read address in accordance with the number of delay stages generated by he processing circuits 3 is not a serious problem. However, if there are two sets of processing circuits operating in parallel and the number of delay stages incidental thereto are different from each other as in the structure of FIG. 5, different write addresses corresponding to respective write data must be provided for the image memories 2b and 2c for writing. In this case, two sets of write address counters should be independently provided. If a larger number of write addresses are necessary, the number of write address counters should also be increased. In a system in which address counter is separately provided external to the image memory, a number of write address counters must be needed with the number corresponding to the number of image memories which can be simultaneously set in the write operation state. Furthermore, the operations of the write address counters are not uniform, causing increase of the size of the hardware and making the control troublesome. Meanwhile, if an independent address counter is appended to every image memory, the trouble of selecting the write address to be employed can be eliminated. However, the setting of the operation state of the write address counter is required, and the hardware becomes larger.
Meanwhile, a method is proposed to compensate for the delay time, in which a circuit capable of making constant the delay time is interposed in the final stage of the pipeline-coupling of the processing circuits. However, in the case where all of the processing circuits operate in parallel, the number of such delay time compensating circuits must be the same as that of the processing circuits, increasing the cost. Furthermore, according to this method, a prescribed delay time must be generated even when the read data of the image memory is directly written in another image memory.